Field of the Invention
The present invention relates to electronics and, more specifically but not exclusively, to schemes for avoiding crowbar current in CMOS micropower circuits.
Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Modern integrated circuit design is dominated by complementary metal oxide semiconductor (CMOS) technology, which combines N-type MOS (NMOS) and P-type MOS (PMOS) transistors in addition to a smaller number of other structures which add design flexibility. Micropower circuits such as bandgaps, low-power oscillators, and other analog circuits operate at bias currents of a few nanoamps or less, which results in slow rise/fall times at internal nodes due to unavoidable parasitic capacitances. The slew rate for a capacitor is set by the equation Δv/Δt=−i/c. At current i=1 nA, an internal node with total capacitance of only c=1 ff has a slew rate Δv/Δt of only 1 v/μs. This is extremely slow compared to sub-100 ps gate delays in modern technologies. (1 μs=1×106 ps.) Within the analog circuitry of a micropower product, the slow transitions are not usually an issue because the designs are developed using long gate-length devices and limiting bias currents to maintain low-power operation. Also, many analog circuits are designed to provide reference voltages or other static voltages or currents for use in other circuits, not to generate switching-circuit operation as is done in clocked circuits. A low-power oscillator required to operate at sub-μA currents presents a challenge due to its output switching behavior required to drive some clocked, digital circuits.
The transition from slow rise/fall times within micropower analog circuitry to fast rise/fall times required to clock digital circuits is the challenge for maintaining very low-power operation. Slow rise/fall times at the gates of digital cells such as inverters can result in very significant time per clock cycle during which both PMOS and NMOS transistors are conducting. The PMOS is sourcing current from the positive supply while the NMOS is sinking current to the negative supply, resulting in significant loss of current needed to drive the load at the gate output. This is known as crowbar current, which is frequently a significant part of CMOS dynamic power, especially when the voltage transitions at the inverter gates are weak. This crowbar current should be eliminated in order to deliver all the driver current to the load and maintain a total current sufficiently low to achieve micropower operation.
For micropower circuits such as oscillators that respond over several orders of magnitude in frequency range, any crowbar reduction scheme should likewise scale in frequency or the scheme will fail over part of the range of operation.
FIG. 1 is a schematic circuit diagram of a conventional inverter 100 that converts an input clock signal CLK applied at the input node IN into an inverted clock signal CLKB appearing at the output node OUT. Inverter 100 comprises a P-type transistor P1 connected in cascode to an N-type transistor N1 between a supply voltage Vdd and a ground voltage Vss. In particular, the source of P1 is connected to Vdd, the drain of P1 is connected to OUT, and the gate of P1 is connected to IN. Similarly, the source of N1 is connected to Vss, the drain of N1 is connected to OUT, and the gate of N1 is connected to IN. If the input clock signal CLK has relatively slow transitions from low to high and from high to low, then, during those transitions, both P1 and N1 will be at least partially on, and a crowbar current will flow between Vdd and Vss through P1 and N1.
FIG. 2 is a schematic circuit diagram of a prior-art inverter 200 that employs cross-coupled logic gates 206a and 206b for reduction of crowbar current, often used in input/output (I/O) drivers handling large capacitive loads. Two signal paths 208a and 208b are generated using inverters 202a and 202b, non-inverting delay cells 204a and 204b, and the cross-coupled NAND gates 206a and 206b to disable the NMOS N1 before the PMOS P1 is turned on to drive the load voltage DOUT high, and conversely to disable the PMOS P1 before the NMOS N1 is turned on to drive the load voltage DOUT low.
As shown in the timing waveforms at the bottom of FIG. 2, when D is initially low, then signal A is forced high by the NAND gate 206b, and signal A/ (i.e., inverted A) is forced low by the inverter 202b. The non-inverting delay cell 204a sends a high state of the signal A delayed to an input of the NAND gate 206a. Since D/ (i.e., inverted D) and A delayed are both high, the output B of the NAND gate 206a is low. Signal B delayed by the non-inverting delay cell 204b at an input of the NAND gate 206b is held low and will remain low for a delay time after B switches state, so node A is held high until the delay time has ended. In this state, PMOS P1 is conducting, NMOS N1 is shut off, and the output DOUT is driven to VDD. The high state of A delayed allows a transition of D to high driving D/ to low to allow a transition of B from low to high without further delay, turning off P1. Since B delayed is still low, A is held high so A/ is low and NMOS N1 is still disabled. After the delay of B, node B delayed rises. Since D and B delayed are now both high, node A is driven low so A/ is driven high to turn on N1 and drive DOUT to ground GND.
This technique has two limitations where a wide frequency range is required. First, the inverters 202a and 202b, the delay elements 204a and 204b, and the logic gates 206a and 206b for this technique have fixed delays for any given set of conditions such as power supply voltage, temperature, and process variation. The fixed delays severely limit the upper range of operation. Second, the cross-coupled logic gates 206a and 206b themselves will have significant crowbar currents if they are driven directly by slow rise/fall time signals.
A second crowbar-elimination technique is described in U.S. patent publication no. 2007/0046330 A1, the teachings of which are incorporated herein by reference. This technique includes resistor and diode components with the claim that (with appropriate selection of device parameters) the time constant of the RC combination of the resistor and the driver gate capacitance will transition one gate turn-on at a substantially slower speed than the turn-off transition at the other gate through a diode. This will reduce the crowbar current. Similar to the first technique, the timing response of these components is fixed by design and can be effective only over a very limited range of frequencies or pulse widths.